VeCS Competing with HDI

Consumers continue to demand electronic devices with increasing functionality, although quantum tunneling hinders further scaling. Smartphones and smartwatches already pack an amazing amount of functionality within these tiny devices. Rush PCB uses microvia technology, facilitating shrinking via structures and high-density interconnect to define routing in dense Printed Circuit Boards (PCBs).  Thereby, it is packing even more functionality within small footprints.

However, designers are under increasing pressure to decrease form factors further and pack even more functionality within single packages. For this purpose, they are exploring newer multi-layer routing architectures.

Microvia Technology

When designers work with only a few layers on a thin board, they usually employ through-hole vias to interconnect layers. As the number of connections increases within a small area, the designer must use unique ways for reaching the inner layers. It should be done while managing board space. It is not possible to route multiple signals through a specific interior layer area using through-hole vias. They are meant only for routing signals between two layers, even when the board has several layers.

Vias, even at microvia sizes, take up unnecessary internal board space. Buried vias do help to some extent, but still take up space when routing between layers not adjacent to one another. Microvias offer better flexibility.

Fabricators create boards with sequential buildup, where they use lasers to place microvia holes in layers instead of using drill bits. They use lasers to drill blind and buried microvias as well, and they plate all these vias using an electrolytic deposition process. Since microvias span only a single layer, connecting across multiple layers needs stacking the microvias or using skip vias for routing the desired connections.

Rush PCB estimates that in HDI PCBs microvias can reduce the total board space by 60-70%. However, microvias are a great help when routing components with high pin densities. In fact, designers can place microvias directly onto the mounting pads for increasing pin densities. Of course, these microvias need filling and plating to prevent them from wicking molten solder during assembly and creating weak electrical connections.

ELIC Technology

ELIC or Every Layer Interconnect routing is a recent innovative development. One big advantage of the ELIC technology is it does not require a core in the center of the board. It can facilitate connections throughout the interior of the board. ELIC is especially suitable for BGA packages for memories, CPUs, GPUs, and other extremely fine-pitch component routing. This technology essentially makes use of copper-filled, stacked microvias for connecting different layers on the board. However, with increasing layout and routing densities, designers are looking for newer technologies for routing between layers in a multi-layer PCB.

Vertical Conductive Structures (VeCS)

VeCS is a promising innovation that increases the routing density of a board tremendously. Designers can place a larger number of tracks between BGA pads using VeCS architecture than they can using microvias or ELIC alone. Therefore, VeCS allows designers to reduce their dependence on multiple interior signal layers when routing HDI boards.

Rather than using round or cylindrical vias, the VeCS architecture makes use of grooves plated with copper for routing into the board surface. The fabricator uses a slightly wider drill to drill holes along the groove. It helps in  leaving straight vertical conductors passing through the inner layers. As no other specialized manufacturing technique or tooling is necessary for VeCS.  It provides the same functionality as ELIC does. This new technique is very useful to designers looking for higher routing density in their HDI boards.

Significance of VeCS

This new technology, VeCS, is a shift from laser-drilled holes and conventionally drilled holes for increasing the densities in vertical connections. Apart from adding more traces in the routing channel, VeCS enhances power distribution to and from the grid array. This allows the reference planes to offer a constant and stable image to the signal layers. Resultantly, it reduces signal distortion and leads to higher data rates.

As the reference plane width under area array packages is much wider for VeCS compared to all other drill or laser processes, designers can lower the interlayer copper weight. Compared to traditional via processes, vertical connections of VeCS have much lower inductance and capacitance. Rush PCB recommends using VeCS architecture to improve signal integrity. It is one of the finest ways to achieve higher bandwidths.

VeCS and its Core Benefits

With VeCS capable of routing signal channels of greater width, designers can afford larger trace widths and higher thicknesses of the dielectric layer. Comparatively, it i better than to  any other innerconnect technology in the industry. For instance, for BGA with pitch 0.8 mm and below, the PCB manufacturing methods require HDI build-up with dual lamination. Additionally, it requires sequential lamination, and small hole drilling methods. All this tends to push up the cost compared to traditional PCBs.

However, the advantages of the VeCS technology becomes more prominent as the BGA pitch goes below 1 mm, and its size increases above 100 I/Os. Even when the BGA pitch goes below 0.5 mm, manufacturers can continue to use conventional manufacturing equipment and materials if they use the VeCS technology.

By increasing the routing channel width, VeCS technology helps designers lower the layer count of most large BGA PCBs. In addition, with VeCS, the designer can place all components in the same position on the topside of the PCB as earlier, use the same materials as with the previous PCBs. While lowering PCB costs and improving the signal integrity performance.

Also Read: Integrity of the Signal in HDI Circuits

Manufacturing Steps for VeCS

Rather than employ an entire hole to connect just two circuits on layers on either side of a PCB, the VeCS technology uses multiple vertical traces through a slot to connect multiple circuits.

The VeCS concept uses peck-drilling to route a cavity or slot into the board, then metallize and plate it to provide the connections. In the final step, the fabricator drills slightly larger holes to create vertical connections between the layers. The vertical connections take up less room than conventionally drilled through-holes do thereby allowing the designer more space for routing the traces.

The manufacturing process for VeCS does not require any change in the conventional multi-layer manufacturing process, apart from adding a few additional steps such as:

  • Drilling or routing a slot between lands for BGA
  • Metallizing the slot
  • Imaging with VeCS breakouts adjacent to the metallized slot
  • Plating the PCB and the slot
  • Etching as normal
  • Creating vertical traces by drilling the metallization

The VeCS process does not involve laser drilling, and the fabricator can use a panel plating process. This makes the VeCS fabrication process very conventional.

Manufacturing Processes for VeCS

VeCS technology can create multiple vertical connections within a slot in a dense area than is possible with the current HDI board technology.

It is possible to combine VeCS slots with microvias if necessary, and like microvias, the slots can form through, blind, or buried connections.

PCB manufacturers can use standard HDI PCB techniques, thereby avoiding capital investments and qualifying new processes.

Drilling Process

The separation between the vertical traces creates a direct barrier to prevent electron migration between adjacent traces. The fabricator can make separation between the adjacent traces to be as accurate as 0.1 mm or less. This is not possible using any other technology at present.

Milling Process

The drilling process creates slots with a minimum width of 0.3 mm. For still thinner slots, fabricators use the milling process, which extends to slots of 0.2 mm or less. Usually the length of the slot varies from a few mm to about 12 mm.  Manufacturers of semiconductor packages employing VeCS can make slots of 0.15 mm and below.

Plating Process

Fabricators use the conventional plating process to plate the slots for the VeCS technology. In fact, plating slots is easier than plating holes as fluid exchange is slots is better. Moreover, the high fluid exchange in slots prevents aspect ratio issues.

Materials and Stackups

Manufacturers can use the regular materials they use for circuit boards for VeCS as well. They can use the same dielectric and copper thicknesses typical to the industry.


Rush PCB suggests using VeCS technology for HDI PCBs, as it does not require any additional capital equipment. In addition, it doesn’t need any medium/high technology PCB manufacturer can start using it with some training. The VeCS technology offers a cost trade-off as the increase in the routing density. It results in a reduction of the number of signal and reference layers or a smaller board.